Memory Hierarchy And Entry Time - Sand Software And Sound

This web page takes a better look on the Raspberry Pi memory hierarchy. Every stage of the memory hierarchy has a capability and speed. Capacities are relatively straightforward to find by querying the working system or studying the ARM1176 technical reference guide. Velocity, however, is just not as straightforward to find and must normally be measured. I exploit a easy pointer chasing technique to characterize the habits of each level in the hierarchy. The approach also reveals the behavior of memory-related efficiency counter events at each degree. The Raspberry Pi implements five levels in its memory hierarchy. The levels are summarized in the table below. The highest level consists of virtual memory pages which are maintained in secondary storage. Raspbian Wheezy keeps its swap space in the file /var/swap on the SDHC card. That is enough space for 25,600 4KB pages. You're allowed as many pages as will fit into the preallocated swap house.



The Raspberry Pi has either 256MB (Mannequin A) or 512MB (Model B) of main memory. That is sufficient house for Memory Wave 65,536 pages or 131,072 physical pages, if all of major memory have been out there for paging. It isn’t all available for person-house packages as a result of the Linux kernel needs house for its own code and data. Linux also supports giant pages, however that’s a separate topic for now. The vmstat command shows details about digital memory usage. Please check with the man page for usage. Vmstat is an efficient tool for troubleshooting paging-associated efficiency issues since it exhibits page in and out statistics. The processor within the Raspberry Pi is the Broadcom BCM2835. The BCM2835 does have a unified stage 2 (L2) cache. However, the L2 cache is dedicated to the VideoCore GPU. Memory references from the CPU facet are routed across the L2 cache. The BCM2835 has two degree 1 (L1) caches: a 16KB instruction cache and a 16KB data cache.



Our evaluation below concentrates on the information cache. The info cache is 4-approach set associative. Each method in an associative set shops a 32-byte cache line. The cache can handle up to four active references to the same set without conflict. If all 4 methods in a set are valid and a fifth reference is made to the set, then a battle happens and Memory Wave Method one of many four methods is victimized to make room for the new reference. The info cache is virtually indexed and physically tagged. Cache strains and tags are stored individually in DATARAM and TAGRAM, respectively. Virtual address bits 11:5 index the TAGRAM and DATARAM. Given a 16KB capacity, 32 byte lines and four methods, there must be 128 sets. Digital address bits 4:Zero are the offset into the cache line. The info MicroTLB translates a digital handle to a bodily address and sends the bodily deal with to the L1 knowledge cache.



The L1 knowledge cache compares the physical handle with the tag and Memory Wave determines hit/miss status and the proper approach. The load-to-use latency is three (3) cycles for an L1 information cache hit. The BCM2835 implements a two stage translation lookaside buffer (TLB) structure for virtual to bodily handle translation. There are two MicroTLBs: a ten entry information MicroTLB and a ten entry instruction MicroTLB. The MicroTLBs are backed by the primary TLB (i.e., the second degree TLB). The MicroTLBs are fully associative. Each MicroTLB translates a digital tackle to a physical tackle in a single cycle when the page mapping information is resident within the MicroTLB (that's, successful in the MicroTLB). The main TLB is a unified TLB that handles misses from the instruction and data MicroTLBs. A 64-entry, 2-approach associative construction. Primary TLB misses are dealt with by a hardware web page table walker. A page desk walk requires at the least one further memory access to seek out the web page mapping info in primary Memory Wave Method.